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GAL18V10
High Performance E2CMOS PLD Generic Array LogicTM Features
* HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 7.5 ns Maximum Propagation Delay -- Fmax = 111 MHz -- 5.5 ns Maximum from Clock Input to Data Output -- TTL Compatible 16 mA Outputs -- UltraMOS(R) Advanced CMOS Technology * LOW POWER CMOS -- 75 mA Typical Icc * ACTIVE PULL-UPS ON ALL PINS * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * TEN OUTPUT LOGIC MACROCELLS -- Uses Standard 22V10 Macrocell Architecture -- Maximum Flexibility for Complex Logic Designs * PRELOAD AND POWER-ON RESET OF REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Standard Logic Speed Upgrade * ELECTRONIC SIGNATURE FOR IDENTIFICATION
8
Functional Block Diagram
I/CLK
RESET
8 OLMC
I/O/Q
I
8 OLMC
I/O/Q
8 OLMC
I
I/O/Q
PROGRAMMABLE AND-ARRAY (96X36)
8 OLMC
I/O/Q
I
10 OLMC
I/O/Q
10 OLMC
I
I/O/Q
8 OLMC
I/O/Q
I
8 OLMC
I/O/Q
I
8 OLMC
I/O/Q
Description
The GAL18V10, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pin PLD. CMOS circuitry allows the GAL18V10 to consume much less power when compared to its bipolar counterparts. The E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. By building on the popular 22V10 architecture, the GAL18V10 eliminates the learning curve usually associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL18V10 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
OLMC
I/O/Q
I
PRESET
Pin Configuration
DIP PLCC
I I 2 I I I I I 8 6 4 I/CLK Vcc 20 18 I/O/Q I/O/Q
I/CLK I I I
I/O/Q
1
20
Vcc I/O/Q
GAL 18V10
5 15
I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q
GAL18V10
Top View
16
I/O/Q I/O/Q
I I I I I/O/Q GND
14 9 11 13
I/O/Q
I/O/Q GND I/O/Q I/O/Q I/O/Q
10
11
I/O/Q
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
18v10_03
1
Specifications GAL18V10
GAL18V10 Ordering Information
Commercial Grade Specifications
Tpd (ns)
7.5
Tsu (ns)
6
Tco (ns)
5.5
Icc (mA)
115 115
Ordering #
GAL18V10B-7LP GAL18V10B-7LJ GAL18V10B-10LP GAL18V10B-10LJ GAL18V10B-15LP GAL18V10B-15LJ GAL18V10-15LP GAL18V10-15LJ GAL18V10B-20LP GAL18V10B-20LJ GAL18V10-20LP GAL18V10-20LJ
Package
20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC 20-Pin Plastic DIP 20-Lead PLCC
10
7
7
115 115
15
8
10
115 115 115 115
20
12
12
115 115 115 115
Part Number Description
XXXXXXXX _ XX X XX
GAL18V10B GAL18V10
Device Name Grade Blank = Commercial
Speed (ns) L = Low Power Power
Package P = Plastic DIP J = PLCC
2
Specifications GAL18V10
Output Logic Macrocell (OLMC)
The GAL18V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to ten product terms (pins 14 and 15), and the other eight OLMCs have eight product terms each. In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The GAL18V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.
AR
D Q CLK SP Q
4 TO 1 MUX
2 TO 1 MUX
GAL18V10 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
Each of the Macrocells of the GAL18V10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC's D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop's /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either "on" (dedicated output), "off" (dedicated input), or "product-term driven" (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array.
3
Specifications GAL18V10
Registered Mode
AR
AR
D
Q
D
Q
CLK SP
Q
CLK SP
Q
ACTIVE LOW S0 = 0 S1 = 0 S0 = 1 S1 = 0
ACTIVE HIGH
Combinatorial Mode
ACTIVE LOW S0 = 0 S1 = 1 S0 = 1 S1 = 1
ACTIVE HIGH
4
Specifications GAL18V10
GAL18V10 Logic Diagram/JEDEC Fuse Map
DIP and PLCC Package Pinouts
1
0 0000 0036 . . . 0324 4 8 12 16 20 24 28 32
ASYNCHRONOUS RESET (TO ALL REGISTERS) 8
OLMC
S0 3456 S1 3457
19
0360 . . . 0648
8
OLMC
S0 3458 S1 3459
18
2
0684 . . . 0972
8
OLMC
SO 3460 S1 3461
17
3
1008 . . . 1296
8
OLMC
S0 3462 S1 3463
16
4
1332 . . . . 1692
10
OLMC
S0 3464 S1 3465
15
5
1728 . . . . 2088
10
OLMC
S0 3466 S1 3467
14
6
2124 . . . 2412
8
OLMC
S0 3468 S1 3469
13
7
2448 . . . 2736
8
OLMC
S0 3470 S1 3471
12
8
2772 . . . 3060
8
OLMC
S0 3472 S1 3473
11
3096 . . . 3384
8
OLMC
S0 3474 S1 3475
9
3420
SYNCHRONOUS PRESET (TO ALL REGISTERS)
3476, 3477 ...
Electronic Signature
... 3538, 3539
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
M S B L S B
5
Specifications GAL18V10B
Absolute Maximum Ratings(1)
Supply voltage VCC ....................................... -0.5 to +7V Input voltage applied ........................... -2.5 to VCC +1.0V Off-state output voltage applied .......... -2.5 to VCC +1.0V Storage Temperature ................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss - 0.5
TYP.3 -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -100 10 0.5 -- 16 -3.2 -130
UNITS V V A A V V mA mA mA
VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2
2.0 -- -- -- 2.4 -- -- -30
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V ftoggle = 15MHz Outputs Open
L -7/-10/-15/-20
--
75
115
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C
6
Specifications GAL18V10B
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAM. TEST COND.1 COM COM COM
DESCRIPTION Input or I/O to Comb. Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynch. Reset of Reg. Asynch. Reset Pulse Duration Asynch. Reset to Clk Recovery Time Synch. Preset to Clk Recovery Time -- -- -- 5.5 0 90.9
-7
-10
-15
-20 UNITS ns ns ns ns ns MHz
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 7.5 5.5 3.5 -- -- -- -- -- -- 6 0 76.9 10 7 3.5 -- -- -- -- -- -- 8 0 55.5 15 10 7 -- -- -- -- -- -- 12 0 41.6 20 12 10 -- -- --
tpd tco tcf2 tsu th
A A -- -- -- A
fmax3
A A
111 111
-- --
105 105
-- --
66.7 66.7
-- --
45.4 62.5
-- --
MHz MHz
twh twl ten tdis tar tarw tarr tspr
-- -- B C A -- -- --
4 4 -- -- -- 8 8 10
-- -- 8 8 13 -- -- --
4 4 -- -- -- 8 8 10
-- -- 10 9 13 -- -- --
6 6 -- -- -- 10 10 10
-- -- 15 15 20 -- -- --
8 8 -- -- -- 15 15 12
-- -- 20 20 20 -- -- --
ns ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
7
Specifications GAL18V10
Absolute Maximum Ratings(1)
Supply voltage VCC ....................................... -0.5 to +7V Input voltage applied ........................... -2.5 to VCC +1.0V Off-state output voltage applied .......... -2.5 to VCC +1.0V Storage Temperature ................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
Recommended Operating Conditions
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss - 0.5
TYP.3 -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -100 10 0.5 -- 16 -3.2 -135
UNITS V V A A V V mA mA mA
VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2
2.0 -- -- -- 2.4 -- -- -50
COMMERCIAL ICC Operating Power
Supply Current
VIL = 0.5V
VIH = 3.0V
L -15/-20
--
75
115
mA
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 C
8
Specifications GAL18V10
AC Switching Characteristics
Over Recommended Operating Conditions
COM PARAMETER COM
TEST COND.1 A A -- -- -- A
DESCRIPTION Input or I/O to Combinatorial Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu +tco) -- -- -- 10 0 50
-15 MIN. MAX. 15 10 7 -- -- --
-20 MIN. MAX. -- -- -- 12 0 41.6 20 12 10 -- -- -- UNITS ns ns ns ns ns MHz
tpd tco tcf2 tsu th
fmax
3
A A
Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback
58.8 62.5
-- --
45.4 62.5
-- --
MHz MHz
twh twl ten tdis tar tarw tarr tspr
-- -- B C A -- -- --
Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynchronous Reset of Register Asynchronous Reset Pulse Duration Asynchronous Reset to Clock Recovery Time Synchronous Preset to Clock Recovery Time
8 8 -- -- -- 10 15 10
-- -- 15 15 20 -- -- --
8 8 -- -- -- 15 15 12
-- -- 20 20 20 -- -- --
ns ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.
Capacitance (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 10 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
9
Specifications GAL18V10
Switching Waveforms
INPUT or I/O FEEDB ACK
INPUT or I/O FEEDB ACK VALID INPUT
VALID INPUT
tsu
th tco
tp d
CO MB INA TO RI AL OUTPUT
CLK
R EG I ST E RE D OUTPUT
Combinatorial Output
1/ fma x (external fdbk)
Registered Output
INPUT or I/O FEEDB ACK
tdis
OUTPUT
ten
CLK
1/ fmax (internal fdbk)
Input or I/O to Output Enable/Disable
R EG I ST E RE D FEED BACK
tcf
ts u
fmax with Feedback
twh
CLK
twl
1/ fma x (w/o fdbk)
Clock Width
INPUT or I/O FEEDB ACK DRIVI NG SP CLK
INPUT or I/O FEEDB ACK DRIVI NG AR
tsu
th
tco
tspr
CLK
tarw
tarr
R EG I ST E RE D OUT PUT
R EG I ST E RE D OUT PUT
tar
Synchronous Preset Asynchronous Reset
10
Specifications GAL18V10
fmax Descriptions
CLK
CLK
LOGIC ARRAY
REGISTER
LOGIC ARRAY
REGISTER
tsu
tco
tcf tpd
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
LOGIC ARRAY
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Times -7/-10 -15/-20 GND to 3.0V 2ns 10% - 90% 3ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT R1 +5V
Input Timing Reference Levels Output Timing Reference Levels Output Load
3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 300 300 300 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
11
Specifications GAL18V10
Electronic Signature
An electronic signature is provided in every GAL18V10 device. It contains 64 bits of reprogrammable memory that can contain userdefined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell.
Output Register Preload
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL18V10 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.
Security Cell
A security cell is provided in every GAL18V10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
Latch-Up Protection
GAL18V10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching.
Input Buffers
GAL18V10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The input and I/O pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. Typical Input Current
I n p u t C u r r e n t (u A )
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
0
-20
-40 -60 0 1.0 2.0 3.0 4.0 5.0
In p u t V o lt ag e ( V o lt s)
12
Specifications GAL18V10
Power-Up Reset
Vcc (min.)
Vcc
tsu
CLK
twl tpr
INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
ACTIVE LOW OUTPUT REGISTER
Device Pin Reset to Logic "1"
ACTIVE HIGH OUTPUT REGISTER
Device Pin Reset to Logic "0"
Circuitry within the GAL18V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some
conditions must be met to provide a valid power-up reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
Feedback PIN
Vcc
(Vref Typical = 3.2V)
Active Pull-up Circuit
Active Pull-up Circuit Tri-State Control Vcc
(Vref Typical = 3.2V)
Vref
Vcc
ESD Protection Circuit
Vref
Vcc
PIN
Data Output
PIN
ESD Protection Circuit
Feedback (To Input Buffer)
Typical Input
Typical Output
13
Specifications GAL18V10
GAL18V10B: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2 1.2 RISE
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
Normalized Tco
FALL
PT L->H
1
Normalized Tsu
1.1
PT H->L
1.1
1.1
PT H->L PT L->H
1
1
0.9
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.2 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
PT H->L
1.2
RISE FALL
1.3
PT H->L PT L->H
Normalized Tpd
Normalized Tco
PT L->H
1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
Normalized Tsu
1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7 -55 -25
0
25
50
75
100
125
Temperature (deg. C)
Temperature (deg. C) Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching
0
Temperature (deg. C)
0
Delta Tpd (ns)
-0.5
Delta Tco (ns)
-0.5
-1
-1
-1.5
RISE FALL
-1.5
RISE FALL
-2 1 2 3 4 5 6 7 8 9 10
-2 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
10 8 10
Delta Tco vs Output Loading
RISE
8
RISE FALL
Delta Tpd (ns)
6 4 2 0 -2 -4 0 50
Delta Tco (ns)
150 200 250 300
FALL
6 4 2 0 -2 -4
100
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
14
Specifications GAL18V10
GAL18V10B: Typical AC and DC Characteristic Diagrams
Vol vs Iol
1 5
Voh vs Ioh
5.25 5 4
Voh vs Ioh
0.75
4.75 4.5
Voh (V)
Vol (V)
3
Voh (V)
0 10 20 30 40 50 60
4.25 4 3.75 3.5 3.25
0.5
2
0.25
1
0 0 10 20 30 40
0
3 0 1 2 3 4
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.2 1.2
Normalized Icc vs Temp
1.4 1.3
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
Normalized Icc
1.1
1.1
1.2 1.1 1 0.9 0.8
1
1
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 -55 -25 0 25 50 75 100 125
0
25
50
75
100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
8 7 -20 0
Input Clamp (Vik)
Delta Icc (mA)
6
4 3 2 1 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Iik (mA)
5
-40 -60 -80 -100 -120 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
15
Specifications GAL18V10
GAL18V10B: Typical AC and DC Characteristic Diagrams
1.3
Normalized Tpd vs. Vcc
1.3
Normalized Tsu vs. Vcc
1.3
Normalized Tco vs. Vcc
1.2
1.2
1.2
Normalized Tco
PT L -> H PT H -> L
Normalized Tpd
Normalized Tsu
1.1
1.1
1.1
1
1
1
0.9
0.9
0.9
0.8
PT H -> L PT L -> H
0.8
0.8
0.7 4.5 4.75 5 5.25 5.5
0.7 4.5 4.75 5 5.25 5.5
0.7 4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs. Temperature
1.3
Supply Voltage (V)
1.3
Normalized Tsu vs. Temperature
Normalized Tco vs. Temperature
1.3
1.2
1.2
1.2
Normalized Tpd
Normalized Tsu
1.1
1
1
Normalized Tco
-25 0 25 50 75 100 125
1.1
1.1
1
0.9
0.9
0.9
0.8
0.8
0.8
0.7 -50
-25
0
25
50
75
100
125
0.7 -55
0.7 -55
-25
0
25
50
75
100
125
Ambient Temperature (C)
Ambient Temperature (C) Delta Tpd vs. Output Loading
1.3
Ambient Temperature (C)
Normalized Icc vs. Vcc
Delta Tpd vs. # of Outputs Switching
0
10
8
1.2
Delta Tpd (ns)
Delta Tpd (ns)
-1
4
Normalized Icc
0 100 200 300 400
6
1.1
1
-2
2
0.9
0
0.8
-3 0 Max. - 8 Max. - 4 Max.
-2
0.7 4.5 4.75 5 5.25 5.5
# of Outputs
Output Loading Capacitance (pf)
Supply Voltage (V)
IOL vs. VOL
250
-150
IOH vs. VOH
1.3
Normalized Icc vs. Temperature
Icc vs. Temperature
200
-100
1.2
Isb vs. Temperature
IOL (mA)
IOH (mA)
150
Normalized Icc
0 1 2 3 4
1.1
1
100
-50
0.9
50
0.8
0 0 1 2 3 4
0
0.7 -55 -25 0 25 50 75 100 125
VOL (V)
VOH (V)
Ambient Temperature (C)
16

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